In "packaging" interconnected chip or chip arrays, wire bondings from the chip or chip array, particularly where there is a high component density, or where bonding pads on chips are closely spaced, are excessively crowded so that there is a real danger that the wire bonds will come into too close contact with each other and present a serious difficulty in maintaining required spacing for the wires and the bonding lands. This is because the conductive patterns converge upon the chips from the printed metalized patterns provided on the single ceramic lamina. The result is overcrowding of the wire conductor or bondings. However, the trend in multiple circuit chip structures, is toward even greater component density, and the conductive patterns on the ceramic package must be wire bonded to the chips of the array.
Thus, the technology trend, headed as it is toward even greater component density, presents serious and thus far unsolved problems of how to achieve the necessary pin outs, from LSI (large scale integrated) arrays though wire bondings to the metalized conductive patterns while still maintaining an industry imposed standard of 10 mil spacings for the pin out wire bonds.